1. Technical Field of the Invention
The present invention relates to phase-locked loops and, more particularly, to an always deterministic phase-locked loop.
2. Background Art
Processors, such as microprocessors, typically have at least one core clock signal and at least one bus clock signal. The ratio of the bus clock frequency to the core clock frequency is sometimes expressed as 1/n or 2/n. For example, in the case in which there are 4 and 1/2 cycles of the core clock signal for every cycle of the bus clock signal, the ratio is 2/9 or 2/n, where n is 9. FIGS. 1 and 2 are examples of 2/n ratios. In the case in which there are only 4 cycles of the core clock signal for every cycle of the bus clock signal, the ratio is 1/4 or 1/n, where n is 4.
Processors typically use a phase-locked loop (PLL) to generate core clock signals. In current Pentium.RTM. II processors, manufactured by Intel Corporation, when the processor is started, the PLL is not synchronized to the bus clock signal. Accordingly, for electronics outside the processor running in a 2/n ratio, it is not known whether a particular bus clock rising edge is aligned or misaligned with the core clock signal. A process triggered by an external event is used to determine the relationship between the core clock and bus clock signals. Referring to FIG. 1, a bus clock signal (busclk) includes some rising edges that are aligned with a core clock signal and some rising edges that are not aligned. The rising edges of the bus clock signal alternate between being aligned and misaligned.
Since the processor's response to external events will be slightly different if they happen on aligned or misaligned edges, the PLL is synchronized before the processor is tested.
A synchronizing external event (e.g., RESET# deassert, SLP# (sleep) deassert#, BPRI# (Priority-agent Bus Request) assert etc.) is used. The PLL samples the phase relationship between the core clock and bus clock signals and stretches the core clock a phase, if necessary, to synchronize the aligned edges with the external event. The term "phase" refers to a section of the signal from one edge to the next (e.g., rising edge to falling edge as illustrated in FIG. 1). This process takes three cycles of the bus clock.
For example, referring to FIGS. 1 and 2, following the rising edge of phase 1 (called the external event phase), the synchronizing external event occurs. Following the rising edge of phase 2 (called the sample phase), the phase relationship between the core clock and bus clock signals are sampled. In FIG. 1, the core and bus clocks are not aligned at the sample phase. In FIG. 2, the core and bus clocks are in aligned at the sample phase. Phase 3 of the bus clock is referred to as the potential stretching phase. Under one scheme, the core clock is stretched by one phase following the rising edge of the potential stretching phase, when the core clock and bus clocks are aligned at the sample phase, and the core clock is not stretched when the core clock and bus clocks are not aligned at the sample phase. Accordingly, in FIG. 1, the core clock is not stretched and in FIG. 2, and the core clock is stretched following the rising edge of the phase 3 of the bus clock. At and following phase 4 of the bus clock, the alignment relationship between the aligned and misaligned edges of the core and bus clocks is deterministic (predictable), although the bus clock alternates between being aligned and unaligned with each cycle.
Disadvantages of the prior art include that in suspend mode of the processor, the alignment relationship between core clock and bus clock is not deterministic. Further, as described, after the processor changes from suspend to normal operating mode, it takes three cycles for the alignment relationship between the core clock and bus clock to be deterministic.